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Proposed Standardization of Chiplet Models for Heterogenous Integration
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"Proposed Standardization of Chiplet Models for Heterogenous Integration"

With the economics of transistor scaling no longer universally applicable, the semiconductor industry faces an inflection point as higher cost, lower yield, and reticle size limitations drive the need for viable alternatives to traditional monolithic solutions.

What we see is the move to innovative packaging technologies to support system-scaling demands and achieve lower system cost. This is driving an emerging trend to disaggregate what typically would be implemented as a single homogeneous, system-on-chip (SoC) ASIC device into discrete, unpackaged ASIC devices, otherwise known as chiplets. Several of these chiplet devices are mounted and interconnected into a single package using high speed/bandwidth interfaces to deliver monolithic or greater performance at reduced cost, higher yield, and lower power with only a slightly larger area than a heterogeneous integrated advanced package.

As fabless semiconductor companies begin to bring these disaggregated chiplets to market, their successful adoption requires the industry to standardize on a set of interface protocols in order to offer plug-and-play compatibility between different suppliers’ chiplets, creating a true open ecosystem and supply chain. Integrating these multi-vendor chiplets into a heterogeneous package assembly will also require chiplet vendors to provide their customers with a standardized set of design model deliverables in order to ensure operability in the end users EDA tool design workflows.

This paper proposes a set of standardized chiplet models that include thermal, physical, mechanical, IO, behavioral, power, signal and power integrity, electrical properties, and test models, as well as documentation to facilitate the integration of the chiplets into a design. Additionally, security traceability assurance is an emerging need to ensure trusted supply chain and operational security of the chiplets and the resulting packaged devices.

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